A solid-state image sensor (image sensor) having a feature of switching the conversion efficiency of floating diffusion (FD) provided in each pixel has been proposed (refer to Patent Document 1).
Since the FD conversion efficiency is define by a value proportional to an inverse of a parasitic capacitance of the FD, the switching of conversion efficiency is achieved by switching of the parasitic capacitance.
The technology according to Patent Document 1 is based on a typical Complementary Metal Oxide Semiconductor (CMOS) image sensor and provides a gate for switching between a first FD having a first capacity and a second FD having a second capacity larger than the first capacity. For making the conversion efficiency higher, the gate is turned off so that the parasitic capacitance to the first FD is minimized, whereas for making the conversion efficiency lower, the gate is turned on to connect the first FD and the second FD with each other so that the parasitic capacitance is maximized.
Furthermore, the technology of Patent Document 1 proposes combining (ZAF) pixels for imaging plane phase difference detection to switch the FD conversion efficiency.
In an image sensor having imaging plane phase difference detection, (ZAF) pixels for imaging plane phase difference detection for autofocus are embedded in a normal pixel array. A ZAF pixel is provided with a light blocking wiring layer for blocking part of incident light as compared to a normal pixel. The light blocking wiring layer has a larger area than other normal wirings owing to the property of blocking light.
In the technology of Patent Document 1, the ZAF light blocking wiring layer is used to form parasitic capacitance as the second capacity for switching the FD conversion efficiency, and switching of the conversion efficiency is achieve by switching the use of the parasitic capacitance.